AI News, Microsoft goes after the barrier to entry for data science with Azure ML
Microsoft goes after the barrier to entry for data science with Azure ML
A month ago, I got a pre-briefing on Microsoft’s Azure Machine Learning with Roger Barga (group program manager, machine learning) and Joseph Sirosh (CVP, Machine Learning).
Yesterday, Microsoft made it available to customers and partners, so now seems like the right time to talk about how it fits into the broader market.
You need to have a deep knowledge of machine learning to get things up and running, whereas Microsoft’s making the effort to curate solid algorithms.
This makes for a nice overlap between Microsoft product and research, the latter of which has some outstanding examples of machine learning (such as the real-time translation from English to Chinese in late 2012 by Rick Rashid).
Some comparisons of data against various distributions to check the best fit and whether that suits the chosen algorithm would be one approach;
They need to figure out how to tell the right stories to the right audiences about ease of use and flexibility, build broader appeal to both forward-leaning and enterprise audiences, and continue to focus on constructing a larger data-science offering on Azure and on Windows (including partners like Hortonworks).
Microsoft Research Blog
Second, Project Brainwave uses a powerful “soft” DNN processing unit (or DPU), synthesized onto commercially available FPGAs. A number of companies—both large companies and a slew of startups—are building hardened DPUs. Although some of these chips have high peak performance, they must choose their operators and data types at design time, which limits their flexibility. Project Brainwave takes a different approach, providing a design that scales across a range of data types, with the desired data type being a synthesis-time decision. The design combines both the ASIC digital signal processing blocks on the FPGAs and the synthesizable logic to provide a greater and more optimized number of functional units. This approach exploits the FPGA’s flexibility in two ways. First, we have defined highly customized, narrow-precision data types that increase performance without real losses in model accuracy. Second, we can incorporate research innovations into the hardware platform quickly (typically a few weeks), which is essential in this fast-moving space.
We architected this system to show high actual performance across a wide range of complex models, with batch-free execution. Companies and researchers building DNN accelerators often show performance demos using convolutional neural networks (CNNs). Since CNNs are so compute intensive, it is comparatively simple to achieve high performance numbers. Those results are often not representative of performance on more complex models from other domains, such as LSTMs or GRUs for natural language processing. Another technique that DNN processors often use to boost performance is running deep neural networks with high degrees of batching. While this technique is effective for throughput-based architectures—as well as off-line scenarios such as training—it is less effective for real-time AI. With large batches, the first query in a batch must wait for all of the many queries in the batch to complete. Our system, designed for real-time AI, can handle complex, memory-intensive models such as LSTMs, without using batching to juice throughput.
- On Monday, March 25, 2019
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