AI News, EDA Challenges Machine Learning

EDA Challenges Machine Learning

Over the past few years, machine learning (ML) has evolved from an interesting new approach that allows computers to beat champions at chess and Go, into one that is touted as a panacea for almost everything.

While there is clearly a lot of hype surrounding this, it appears that machine learning can produce a better outcome for many tasks in the EDA flow than even the most seasoned architects and designers can generate.

Since design decisions need to be made on reliable data for chips to work, uncertainty in the level of accuracy makes designers reject machine learning methods and move back to more brute-force techniques, even though they may take way longer to run and cover less of the design space.”

The second category of machine learning, known as unsupervised learning, is also unlikely to be directly useful, as its primary utility is in identifying unknown similarities in massive groups of elements.

“Known as reinforcement learning, this process learns by creating output, analyzing the results based on various metrics, recommending changes intended to improve the results, and then going around the loop again.”

Source: Semiconductor Engineering This sequence will sound very familiar to engineers who work to make their chips converge to the correct implementation of a design rule that also meets frequency, area, power and performance goals.

“If, or more accurately, when a design methodology is encapsulated into a closed loop, such that the methodology can be allowed to run many iterations freely, reinforcement learning can autonomously identify optimal solutions that were unlikely to have occurred to human design engineers,”

It will be critical to be able to vary the compute effort versus quality of results (QoR), such that the iterative analysis can run a very large number of iterations early in the learning process, exploring a very wide design space.

“There is machine learning inside, which means there is no change in the human interface, or there is machine learning outside, which is a more transformational change in how the human is going to interact with the process.”

“Machine learning outside is about finding out what your expert is doing and expediting the time it takes them to close timing, or between architecture freeze and signoff, or how to design the power grid.

Adaptive learning: The algorithm must be able to actively target areas of interest, areas of high uncertainty, and areas where behaviors are shifting, and to fill in data in these areas to actively boost accuracy.

Dyck believes that if designers have sufficiently accurate results, the level of accuracy is known, and the machine learning predictions are verifiable, then they can make dependable engineering decisions—and they can defend those decisions in design reviews.

“Not just on the algorithm development side, but on the user experience side in order to make it clear to designers how accurate results are and to clearly show that the results are verified in a way they can understand.

Dyck provides some examples including the wider voltage domain for finFETs, meaning you have to look at 7-10 voltages rather than 3 for legacy nodes, the added back-biasing for FD-SOI, and multiple extraction conditions caused by double patterning, among other things.

“A typical process/voltage/temperature (PVT) space at legacy nodes might include just 3 process conditions, 3 voltages, and 3 temperatures, while at modern nodes, it’s common to run 50 to 100 PVT and extraction conditions,”

“Using a cost function based on power or total energy, one can use machine learning trained on existing designs on the current node to optimize new designs on the same node,”

“ML techniques have been used extensively to improve yield through wafer map failure diagnosis, equipment monitoring / tracking / diagnosis, and process optimization,”

“While it takes many Monte Carlo simulations to address variability of processes or design attributes and can be very time consuming, ML techniques have been proven to predict the sample inputs needed to achieve the prediction of output variability and reduce the run time.”

“ML can be used to generate the interconnect for a new SoC without any intervention from a design engineer, other than setting the design goals and creating the initial physical floorplan—assuming, of course, that a solution is possible,”

“The iterating design methodology can generate many possible interconnect candidates, implement them through to a layout rule correct design, analyze the results and make changes, looping until a solution is found or the algorithm decides that further work will not be useful without changing input parameters.

On a smaller scale, the effectiveness of individual methods could be further improved by combining advanced data analytics with new verification workflows, such as formal verification methods.

In particular, gathering performance data during runtime over several episodes allows building predictive models for fine-tuning heuristics or projecting tool runtimes and verification results.

“Capsules introduce a new building block that can be used in deep learning to better model hierarchical relationships inside of internal knowledge representation of a neural network.

While processing an entire SoC may always be a challenging task, it is very likely that the type of partitioning that human engineers use to make the vast seas of data comprehensible will lead to a number of locally optimal solutions that, when combined, yield a near-optimal global result.”

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