AI News, Data Science Applications in Semiconductor Manufacturing
Data Science Applications in Semiconductor Manufacturing
In this post, we will look at how data science can be used to improve mechanical and materials engineering in the semiconductor manufacturing industry by summarizing the work that Pivotal’s Data Science team did for a real-world customer.
While working with a semi-conductor company, we set out to systematically identify defect patterns on a wafer earlier in manufacturing, and tie them back to the production process for root cause analysis.
The wafers are tested to characterize the dies on the wafer as good or bad, generating a wafer bin map (WBM) that shows the specific test for which a die has failed.
The Process Illustrated in the diagram below, the process is a multi-step de-noising, preprocessing, feature extraction, dimensionality reduction, outlier detection, and clustering to show how yield and profitability are improved.
To reduce the noise, we used a median filtering technique, where the median value of die failures in a bin neighborhood is used to replace the central bin value.
Starting from top left position to bottom right position, we mapped out a 1519-dimensional binary feature vector, representing all the positions of die failures on the wafer.
A k-means clustering algorithm, available through the newly incubating Apache MADlib project, is used to group the wafers into 20 clusters with random initial seeding.
[H2]Next Steps Once we established the defect patterns from the wafers, we were then able to correlate these failures back to the specific process parameters of this manufacturer for root cause analysis and we were able to generally improve profitability of this manufacturing process.
is a thin slice of semiconductor material, such as a crystalline silicon, used in electronics for the fabrication of integrated circuits and in photovoltaics for conventional, wafer-based solar cells.
The wafer serves as the substrate for microelectronic devices built in and over the wafer and undergoes many microfabrication process steps such as doping or ion implantation, etching, deposition of various materials, and photolithographic patterning.
In this process, a cylindrical ingot of high purity monocrystalline semiconductor, such as silicon or germanium, called a boule, is formed by pulling a seed crystal from a 'melt'.
Donor impurity atoms, such as boron or phosphorus in the case of silicon, can be added to the molten intrinsic material in precise amounts in order to dope the crystal, thus changing it into n-type or p-type extrinsic semiconductor.
The diameter has gradually increased to improve throughput and reduce cost with the current state-of-the-art fab using 300 mm, with a proposal to adopt 450 mm.
unit wafer fabrication step, such as an etch step, can produce more chips proportional to the increase in wafer area, while the cost of the unit fabrication step goes up more slowly than the wafer area.
Lithographer Chris Mack claimed in 2012 that the overall price per die for 450 mm wafers would be reduced by only 10–20% compared to 300 mm wafers, because over 50% of total wafer processing costs are lithography-related.
Converting to larger 450 mm wafers would reduce price per die only for process operations such as etch where cost is related to wafer count, not wafer area.
Mark LaPedus of semiengineering.com reported in mid-2014 that chipmakers had delayed adoption of 450 mm “for the foreseeable future.” According to this report some observers expected 2018 to 2020, while G.
The step up to 300 mm required major changes, with fully automated factories using 300 mm wafers versus barely automated factories for the 200 mm wafers.
These major investments were undertaken in the economic downturn following the dot-com bubble, resulting in huge resistance to upgrading to 450 mm by the original timeframe.
On the ramp up to 450 mm are that the crystal ingots will be 3 times heavier (total weight a metric ton) and take 2–4 times longer to cool, and the process time will be double.
In general, this is a computationally complex problem with no analytical solution, dependent on both the area of the dies as well as their aspect ratio (square or rectangular) and other considerations such as scribeline size and the space occupied by alignment and test structures.
Refinements of this simple formula typically add an edge correction, to account for partial dies on the edge, which in general will be more significant when the area of the die is large compared to the total area of the wafer.
Studies comparing these analytical formulas to brute-force computational results show that the formulas can be made more accurate, over practical ranges of die sizes and aspect ratios, by adjusting the coefficients of the corrections to values above or below unity, and by replacing the linear die dimension
Scoring the wafer along cleavage planes allows it to be easily diced into individual chips ('dies') so that the billions of individual circuit elements on an average wafer can be separated into many individual circuits.
Silicon wafers are generally not 100% pure silicon, but are instead formed with an initial impurity doping concentration between 1013 and 1016 atoms per cm3 of boron, phosphorus, arsenic, or antimony which is added to the melt and defines the wafer as either bulk n-type or p-type.
Wafer Service Overview
In electronics, a wafer is a thin slice of semiconductor material used to fabricate integrated circuits or other microdevices1.
Prior to the actual creation of the raw wafer itself, numerous steps can be taken to improve the performance of the resulting transistors, including processes to improve electronic mobility or reduce parasitic effects2.
Raw wafers can be engineered by growing an ultrapure silicon layer via epitaxy (the deposition of an overlayer on a crystalline substrate, with the overlayer being in registry with the substrate3 ).
Multiple layers of interconnected devices can then be further interconnected by etching tiny holes in the insulating material and depositing tungsten or similar materials into these holes via chemical vapor deposition5.
Wafer backgrinding, also referred to as 'backlap' or 'wafer thinning,' is a process in which the backside of a wafer is ground down, producing a thinner wafer that allows more layers and a higher density of integrated circuits to fit in a smaller package.
In the lamination stage, a protective tape is applied over the surface of the wafer to protect against mechanical damage and contamination by grinding fluid and debris6.
After backgrinding and any post-grinding procedures, the glass substrates are removed via laser debonding7 Laminated wafers are then loaded into wafer cassettes, which in turn are loaded into an automated backgrinding machine.
This machine uses a robotic arm to pick up the wafers and position them, back side facing up, under high precision, computer-controlled grinding wheels.
To achieve the ultra thin thicknesses or specific surface roughness requirements, multiple grind wheels may be employed, starting with a coarse grit and progressing to wheels with finer and finer grits8 .
SEZ etch and CMP polishing are wet chemical processes designed to gently remove silica material without placing additional mechanical stress on wafers.
The laser dicing process is an exception to this, as instead of a metal frame, the wafer is secured to an underlying carrier membrane that expands after the laser has made its cuts, inducing fracture and separating the dies10 .
Essentially, die sorting is the process of removing known good die from a diced, electrical tested and visually inspected wafer and placing them into packaging, such as waffle packs, Gel-Paks®, or tape and reel, preparing them for further processing steps.
These systems use automated visual die maps based on information gleaned during electrical test and wafer inspection to locate passing die;
1http://en.wikipedia.org/wiki/Wafer_%28electronics%29 2http://en.wikipedia.org/wiki/Semiconductor_device_fabrication#Front-end-of-line_.28FEOL.29_processing 3http://en.wikipedia.org/wiki/Epitaxy 4 http://en.wikipedia.org/wiki/Semiconductor_device_fabrication#Back-end-of-line_.28BEOL.29_processing 5http://en.wikipedia.org/wiki/Back_end_of_line 6http://www.siliconfareast.com/backgrind.htm 7http://www.syagrussystems.com/3M-Wafer-Support-System 8http://www.electroiq.com/articles/ap/print/volume-11/issue-3/features/the-back-end-process-step-3-wafer-backgrinding.html 9http://www.syagrussystems.com/wafer-backgrinding 10 http://en.wikipedia.org/wiki/Wafer_dicing 11http://www.syagrussystems.com/die_visual_inspection.php
Semiconductor device fabrication
Semiconductor device fabrication is the process used to create the integrated circuits that are present in everyday electrical and electronic devices.
Technology nodes, also known as 'process technologies' or simply 'nodes', are typically indicated by the size in nanometers (or historically micrometers) of the process's gate length.[clarification needed]
The entire manufacturing process, from start to packaged chips ready for shipment, takes six to eight weeks and is performed in highly specialized facilities referred to as foundries or fabs.
typical wafer is made out of extremely pure silicon that is grown into mono-crystalline cylindrical ingots (boules) up to 300 mm (slightly less than 12 inches) in diameter using the Czochralski process.
In semiconductor device fabrication, the various processing steps fall into four general categories: deposition, removal, patterning, and modification of electrical properties.
Another method, called silicon on insulator technology involves the insertion of an insulating layer between the raw silicon wafer and the thin layer of subsequent silicon epitaxy.
Front-end surface engineering is followed by growth of the gate dielectric (traditionally silicon dioxide), patterning of the gate, patterning of the source and drain regions, and subsequent implantation or diffusion of dopants to obtain the desired complementary electrical properties.
In dynamic random-access memory (DRAM) devices, storage capacitors are also fabricated at this time, typically stacked above the access transistor (the now defunct DRAM manufacturer Qimonda implemented these capacitors with trenches etched deep into the silicon surface).
This occurs in a series of wafer processing steps collectively referred to as BEOL (not to be confused with back end of chip fabrication, which refers to the packaging and testing stages).
The insulating material has traditionally been a form of SiO2 or a silicate glass, but recently new low dielectric constant materials are being used (such as silicon oxycarbide), typically providing dielectric constants around 2.7 (compared to 3.82 for SiO2), although materials with constants as low as 2.2 are being offered to chipmakers.
More recently, as the number of interconnect levels for logic has substantially increased due to the large number of transistors that are now interconnected in a modern microprocessor, the timing delay in the wiring has become so significant as to prompt a change in wiring material (from aluminum to copper interconnect layer) and a change in dielectric material (from silicon dioxides to newer low-K insulators).
CMP (chemical-mechanical planarization) is the primary processing method to achieve such planarization, although dry etch back is still sometimes employed when the number of interconnect levels is no more than three.
For example, thin film metrology based on ellipsometry or reflectometry is used to tightly control the thickness of gate oxide, as well as the thickness, refractive index and extinction coefficient of photoresist and other coatings.
In certain designs that use specialized analog fab processes, wafers are also laser-trimmed during the testing, in order to achieve tightly-distributed resistance values as specified by the design.
Good designs try to test and statistically manage corners (extremes of silicon behavior caused by a high operating temperature combined with the extremes of fab processing steps).
Most fabrication facilities employ exhaust management systems, such as wet scrubbers, combustors, heated absorber cartridges, etc., to control the risk to workers and to the environment.
- On Friday, October 18, 2019
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